Modeling structural damage to line/space patterns from high-speed droplet impact in particulate cleaning on patterned wafers

<!-- START_ABSTRACT --> <p> As semiconductor devices scale down to sub-5 nm nodes, the removal of nanoscale contaminants without damaging patterns has become increasingly critical. While physical cleaning methods such as liquid jet spray offer advantages over chemical cleaning, balancing high particle removal efficiency (PRE) with structural integrity remains challenging. In this study, a predictive model was developed for structural damage in silicon line/space patterns subjected to high-speed droplet impact. The model evaluates the principal stress induced in line sidewalls based on pattern geometry and impact conditions, introducing the concept of a damage radius to estimate the extent of damage. Experimental validation was conducted using Ti nanoparticles (10–60 nm) deposited on Si patterns with various geometries and cleaned at droplet velocities of 33–84 m/s. The predicted damage radius showed reasonable agreement with the experimental observations. Among the geometric parameters of line structures, aspect ratio was found to be the dominant factor influencing structural damage, whereas line spacing had minimal effect. In contrast, line spacing significantly affected cleaning performance. Finally, a universal parameter governing damage rate was identified, clarifying its functional dependence on impact and structural parameters. </p> <!-- END_ABSTRACT --> <!-- START_TEMPLATE --> <ul> <li> Source: </li> <li> Tags: </li> </ul> <!-- END_TEMPLATE -->